Increasing the speed of digital devices using the ASMD-FSMD method using non-blocking operators

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Abstract

The ASMD-FSMD method for designing digital devices is considered, which consists of constructing a block diagram of an algorithmic state machine with a data path (ASMD), which describes the behavior of the device, and creating project code in Verilog in the form of a finite state machine with a data processing path. (finite state machine with datapath – FSMD). One of the directions for the development of the ASMD-FSMD methodology is the use of features of the hardware description language (HDL). A hypothesis has been put forward: in the ASMD-FSMD technique, it is possible to apply several non-blocking assignment operators to the same variable in one synchronization cycle, which will lead to an increase in device performance. The hypothesis put forward was investigated in the design of synchronous multipliers that implement the classical multiplication algorithms c and d. Experimental studies have confirmed the validity of the put forward hypothesis, while the speed of the multipliers increases two to three times, and the cost of implementation in most cases decreases compared to the traditional approach.

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About the authors

V. V. Solov’ev

Bialystok University of Technology

Author for correspondence.
Email: valsol@mail.ru
Poland, Bialystok, 15-351

A. S. Klimovicz

Bialystok University of Technology

Email: valsol@mail.ru
Poland, Bialystok, 15-351

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Supplementary files

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2. Fig. 1. The AMD block.

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3. Fig. 2. Operating device of the synchronous multiplier c.

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4. Fig. 3. The control device of the synchronous multiplier c in the form of a graph of a finite automaton of the Mile type.

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5. Fig. 4. The ASMD scheme of the c multiplication algorithm. The simulation results of the mult_c_Mealy_FSMD project in the Quartus Prime system are shown in Fig. 5. It can be seen that the multiplication of 4-bit numbers is actually performed in five clock cycles of the clk clock signal. For comparison, Figure 6 shows the simulation results of a synchronous multiplier implementing the c multiplication algorithm, which was designed using traditional technology. As you can see, the multiplication of 4-bit numbers is performed in nine clock cycles.

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6. Fig. 5. Simulation results of the multiplier, designed according to the ASTM D-SMD method (a) and built according to the traditional method (b).

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7. Fig. 6. Coefficients (number of times) of speed increase for each example in the Quartus system.

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8. Fig. 7. Coefficients (number of times) of speed increase for each example in the Vivado system.

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9. Fig. 8. Coefficients (number of times) of reducing the cost of implementation for each example in the Vivado system.

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