Synthesis of a serial-to-parallel converter based on the GaAs D-mode phemt technology using the evolutionary algorithms

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Abstract

A new approach to the synthesis of a serial-to-parallel converter (SPC) based on the 0.25 μm GaAs D-mode pHEMT process is presented. Evolutionary algorithms application to solve SPC synthesis problem is shown. Solution, that have same structure as designer solution but with less power consumption, propagation delay and theoretically less total area is obtained. Its operability has been proved by comparison between simulated and measured data. Synthesis process takes up to 12 hours.

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About the authors

D. V. Bilevich

Tomsk State University of Control Systems and Radioelectronics

Email: andrei.salnikov@main.tusur.ru
Russian Federation, Lenina st., 70, Tomsk, 634050

A. S. Salnikov

Tomsk State University of Control Systems and Radioelectronics

Author for correspondence.
Email: andrei.salnikov@main.tusur.ru
Russian Federation, Lenina st., 70, Tomsk, 634050

A. E. Goryainov

Tomsk State University of Control Systems and Radioelectronics

Email: andrei.salnikov@main.tusur.ru
Russian Federation, Lenina st., 70, Tomsk, 634050

I. M. Dobush

Tomsk State University of Control Systems and Radioelectronics

Email: andrei.salnikov@main.tusur.ru
Russian Federation, Lenina st., 70, Tomsk, 634050

A. A. Kalentyev

Tomsk State University of Control Systems and Radioelectronics

Email: andrei.salnikov@main.tusur.ru
Russian Federation, Lenina st., 70, Tomsk, 634050

A. A. Popov

Tomsk State University of Control Systems and Radioelectronics

Email: andrei.salnikov@main.tusur.ru
Russian Federation, Lenina st., 70, Tomsk, 634050

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Supplementary files

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2. Fig. 1. Block diagram of the digital control driver.

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3. Fig. 2. Schematic diagram of a shift register based on NOR elements.

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4. Fig. 3. Variations of inverter circuit implementation.

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5. Fig. 4. Block diagram of the genetic algorithm.

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6. Fig. 5. Graph of the penalty function.

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7. Fig. 6. The resulting schematic diagram of the inverter.

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8. Fig. 7. Microphotograph of the manufactured driver bit.

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9. Fig. 8. Diagram of the measuring setup: 1 – oscilloscope, 2 – coaxial connection, 3 – arbitrary waveform generator, 4 – coaxial cable, 5 – triaxial cable, 6 – crystal, 7 – low-frequency probe.

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10. Fig. 9. Characteristics of a four-bit shift register: 1 – modeling; 2 – measurement.

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11. Fig. 10. Characteristics of one bit of the control driver: 1 – modeling; 2 – measurement.

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